Computer Science Test 8 Nddc Scholarship

A microprogram is a sequence of elementary instructions, known as microinstructions, stored in a special control memory. These microinstructions are used to implement the machine-level instructions of a computer's instruction set.
When a CPU executes a high-level assembly instruction, the control unit reads the corresponding microprogram to trigger the specific sequence of control signals required to perform the task. Essentially, microprogramming serves as a bridge between the high-level hardware architecture and the low-level electronic pulses that drive the CPU.

Interrupt Latency refers to the interval from the moment an interrupt signal is generated by a hardware device until the CPU begins executing the first instruction of the corresponding Interrupt Service Routine (ISR).
It includes the time the CPU takes to complete the execution of its current instruction, perform context switching, and identify the source of the interrupt. Low interrupt latency is critical in real-time systems where the hardware must react almost instantaneously to external events to ensure system stability and performance.

The Microprogram Controller (also known as a microsequencer) is a functional unit that generates the addresses for the next microinstruction to be fetched from control memory.
It determines the order of execution, handling both sequential flows and branching logic within the microprogram. By managing the program counter for the control memory, it ensures that the correct hardware control signals are activated in the precise order necessary to complete a machine-level operation.

Virtual Memory is a memory management technique that provides an 'idealised' abstraction of the storage resources actually available on a given machine, allowing the system to use disk space as an extension of RAM.
It is not an Input/Output (I/O) communication technique. In contrast, Programmed I/O, Interrupt-driven I/O, and DMA are all specific methods designed to facilitate the transfer of data between the central processor (or main memory) and external devices like keyboards, hard drives, or network interfaces.

An Overrun Error occurs in serial communication when a receiver's buffer is full and a new character arrives before the CPU has had a chance to read the previous data.
Because the buffer can only hold a specific amount of information, the old, unread character is lost as it is replaced by the new one. This typically happens when the baud rate (speed) of transmission exceeds the processing speed of the receiving hardware or software, leading to a loss of data integrity in the communication stream.

A Software Poll is an interrupt-handling method where a single, common interrupt request line is used by multiple I/O modules. When an interrupt is triggered, the CPU executes a specialized routine that 'polls' (queries) each module one by one in a specific order of priority.
Upon finding the module that requested the service, the CPU branches to the specific Interrupt Service Routine (ISR) for that device. While simple to implement in hardware, it is slower than hardware-based methods like vectored interrupts or daisy chaining.

An I/O Port serves as a physical and logical gateway that allows a computer to communicate with external peripheral devices such as printers, scanners, or keyboards.
The port provides the necessary electrical and protocol translation so that data traveling on the internal system bus can be understood by the external hardware. Essentially, the I/O port acts as an addressable location where the CPU can send or receive data destined for hardware outside the core system architecture.

Isolated I/O (also called I/O-mapped I/O) uses a distinct address space for I/O devices, separate from the address space used for main memory. The CPU typically uses special instructions, such as 'IN' and 'OUT', to access these ports.
This is different from Memory-Mapped I/O, where I/O devices are assigned addresses within the same range as the RAM, allowing standard memory instructions to be used for communication. Isolated I/O ensures that the full memory address range remains available for system RAM.

To insert 35 into a max heap, we follow these steps:
1. Place 35 at the end of the array: [40, 30, 20, 10, 15, 16, 17, 8, 4, 35].
2. Compare 35 with its parent (the value at index \((i-1)/2\)). Here, 35 is at index 9, so its parent is at index 4 (value 15).
3. Since 35 > 15, we swap them: [40, 30, 20, 10, 35, 16, 17, 8, 4, 15].
4. Now compare 35 (at index 4) with its new parent at index 1 (value 30).
5. Since 35 > 30, we swap them again: [40, 35, 20, 10, 30, 16, 17, 8, 4, 15].
6. Finally, compare 35 (at index 1) with its parent at index 0 (value 40). Since 35 < 40, the process stops. The final array is 40, 35, 20, 10, 15, 16, 17, 8, 4, 30 because the swap only occurred with the parent nodes until the heap property was satisfied.

Partial decoding (also known as incomplete decoding) is a method used to simplify the circuitry of an address decoder. Instead of using all available address lines to uniquely identify a memory or I/O location, some lines are left unconnected or ignored.
While this reduces the number of logic gates required, it creates 'mirrored' or 'alias' addresses, where a single physical device appears at multiple locations within the address space. This is often used in low-cost systems where the full addressable range of the CPU is not required by the actual hardware attached.